FLYBACK CALCULATIONS - PART VIII

The following figures are for a flyback AC-DC converter that was designed as a demo circuit for purposes of showing circuit analysis and simulation. The design is not intended to be suitable for use as an actual production converter and it would not necessarily meet requirements for agencies such as UL or other testing and certification agencies. As shown in Fig. the converter appears to have a secondary side isolated from the primary but in the actual simulations both primary and secondary are connected to the SPICE zero or ground node to simplify simulation convergence. The figures shown in order of appearance are first the overall loop gain versus frequency, the control-to-output gain versus frequency, and the simulation schematic for the converter design. Click on the figures for a larger view.






Fig. 1 shows a so-called universal input AC-DC converter. The converter design shown is supposed converter AC 50-60 HZ, 90 to 265 VAC input to a 5 volt output at 1 amp. The switching frequency is approximately 100KHZ. The circuit shown is an actual simulation schematic which shows that the circuit will operate as desired and is stable with a load transient from a minimum load of 10 MA to 1AMP as is shown in the simulation result diagram below Fig. 1. Click on the figures for a larger view.

In the design we have used the principles discussed in our previous posts but it should be noted that in some cases component values are adjusted to give improved simulation results (The converter has different specifications than the examples in previous posts.)

The main purpose of this post is to review the feedback circuit calculations.

The converter is a current mode control type that operates in discontinuous current mode throughout its operating range.

The current control factor is

K = Ilim / Vfbsat = 1 / 5.8 = 0.172

The zero in the control-to-output gain is

wz = 1 / ( Rc * Co ) = 1 / ( 0.09 * 6.8 *10^-4 ) = 16340 radians or 2600HZ

Next, we compute the worst case control-to-output gain response pole at minimum load (maximum resistance load)

wp = 2 / ( RLmax * Co ) = 2 / ( 500 * 6.8 * 10^-4 ) = 5.882 radians or approx 1HZ.

To make our equations a little easier to type here let me make the following substitutions:

Z1 = 1 + ( S / wz ) where S is the complex operator = j * 2 * Pi * f (using only the imaginary component of S in this work.)

P1 = 1 + ( S / wp )

The values of Z1 and P1 are only dummy variables and not actual frequencies, but their values will be different at different frequencies. Also note here that because we always operate in discontinuous current mode (DCM), we do not have to worry about a right-half plane zero which would otherwise be present if we were operating in continuous current mode (CCM.)

We can now type a simple equation for the control-to-output gain as a function of frequency as follows:

Gco = ( Vo / VFB ) * ( Z1 / P1 )

where Vo is the nominal output voltage ( 5 volts ) and VFB is the nominal feedback voltage ( 2.5 volts .) A plot of the control-to-output gain is shown in the post.

Next we have a simple compensation network that is similar to the ones used in most flyback converters of this type. The purpose of the compensation network is to make the system stable with a reasonable control band-width and known feedback characteristics, such as cross-over frequency, phase and gain margins.

First we compute the constant gain factor K as

K = RB / ( R1 * RD * CF ) = 1000 / ( 5360 * 100 * 1 * 10^-6 ) = 1866

where RB is the PWM controller IC feedback input impedance (we added a 1K to ground at the ouput of opto-coupler to establish a known value for this quantity.) RD is the feedback amplifier IC collector resistance, and CF is the compensation capacitance for this amplifier.

We need to have a compensation zero to help cancel the converter pole at 1 HZ. But the compensation pole will be set at approximately 15HZ:

wzc = 1 / ( ( RF + R1 ) * CF ) = 1 / ( ( 5100 + 5360 ) * 1 *10^-6 ) = 95.6 radians
or 15.2 HZ.

Also we need to set a compensation pole. We will set this pole at a relatively high frequency in order to flatten over-all loop gain and establish reasonable bandwidth.

wpc = 1 / ( RB * CB ) = 1 / ( 1000 * 1 * 10^-8 ) = 100000 radians

or 15920 HZ ( still well below the switching frequency of 100KHZ.)

Now for convenience in typing the compensation equation we will set some dummy variables as

Zc = 1 + ( S / wzc )

and

Pc = 1 + ( 1 / wpc )

We can now write a simple equation for the compensation gain as a function of frequency as

Gc = - ( K / S ) * ( Zc / Pc )

In the above equation we note that the negative sign is because we are using negative feedback in the compensation circuit to control the converter.

Now it is known that the overall loop gain, that is the gain of the converter from its input around to the feedback input at the IC controller can be computed from the product of the control-to-output gain and the compensation gain as

Gol = Gco * Gc

The results of the calculation vs. frequency is shown in the chart for the loop gain. The calculations can be done by math programs such as Mathcad, etc.

You will note that the loop gain has a cross-over frequency of approximately 40HZ (which could probably be improved a lot with some improvements to the compensation circuit.) The loop gain at DC is pretty good at over 50DB and the cross-over slope is -20db per decade indicating absolute stability (this is also verified by SPICE simulation of the closed loop circuit of Fig. 1.) The phase shift is a little over 70 degrees at crossover which gives us a phase margin of 110 degrees which also indicates absolute stability. So this converter is a relatively low bandwidth design but should be very stable over all operating conditions that wre within its specifications. The fact that it operates in DCM also helps simplify stabilization, but this is not to say that we should always operate in DCM. In fact, if the converter had been designed as a CCM type, it would be capable of more power and peak ripple current in the output filter capacitor could be reduced.

FLYBACK CALCULATIONS - PART VII

In this section we will discuss the snubber network for the transistor switch on the primary side of the converter (see Fig.1. Click on the figure to see a larger view.) First an estimate is made for the voltage spike that is to be snubbed as 2.5 times the reflected voltage from the secondary as

Vsn = 2.5 * VRO

With VRO previously determined to be 350 volts (see previous posts), we have

Vsn = 875 volts

Next we use this estimate to calculate an approximate value for the power dissipated in the snubber network.

Psn = 0.5 * Fs * Llk * Idspeak^2 * Vsn / (Vsn -VRO)

where Fs is the switching frequency, Llk is the transformer leakage inductance, and Idspeak is the peak transistor switch current. Our calculation results in

Psn = 0.316 watts

where the data we used is from our design example as

Fs = 100KHZ
Llk = 141 microhenry
Idspeak = 0.164

Now we can calculate a rough estimate of what the snubber resistor value should be (usually it is necessary to change the value based on actual snubber network performance but it gives us a starting point.)

Rsn = Vsn^2 / Psn = 2.4 megohm

(In the actual design, this resistor was changed to 360K.)

Using the 2.4 megohm value for the snubber resistor we will calculate the ripple voltage on the capacitor we have


dVsn = Vsn / ( Csn * Rsn * Fs ) = 3.6 volts

with Csn set to 0.001 microfarad. Note that if the value of Csn is set too hihg the operation of the flyback converter will not work well, e.g., values above 0.01 microfarad usually do not provide good results depending on the other values used in the design such as the primary inductance value. Remember that the primary inductance and the snubber capacitor form a "tank" circuit that can resonate and this is not usually desirable in a standard flyback converter.

We now have a preliminary design for the snubber network.