FLYBACK CALCULATIONS - PART VIII

The following figures are for a flyback AC-DC converter that was designed as a demo circuit for purposes of showing circuit analysis and simulation. The design is not intended to be suitable for use as an actual production converter and it would not necessarily meet requirements for agencies such as UL or other testing and certification agencies. As shown in Fig. the converter appears to have a secondary side isolated from the primary but in the actual simulations both primary and secondary are connected to the SPICE zero or ground node to simplify simulation convergence. The figures shown in order of appearance are first the overall loop gain versus frequency, the control-to-output gain versus frequency, and the simulation schematic for the converter design. Click on the figures for a larger view.






Fig. 1 shows a so-called universal input AC-DC converter. The converter design shown is supposed converter AC 50-60 HZ, 90 to 265 VAC input to a 5 volt output at 1 amp. The switching frequency is approximately 100KHZ. The circuit shown is an actual simulation schematic which shows that the circuit will operate as desired and is stable with a load transient from a minimum load of 10 MA to 1AMP as is shown in the simulation result diagram below Fig. 1. Click on the figures for a larger view.

In the design we have used the principles discussed in our previous posts but it should be noted that in some cases component values are adjusted to give improved simulation results (The converter has different specifications than the examples in previous posts.)

The main purpose of this post is to review the feedback circuit calculations.

The converter is a current mode control type that operates in discontinuous current mode throughout its operating range.

The current control factor is

K = Ilim / Vfbsat = 1 / 5.8 = 0.172

The zero in the control-to-output gain is

wz = 1 / ( Rc * Co ) = 1 / ( 0.09 * 6.8 *10^-4 ) = 16340 radians or 2600HZ

Next, we compute the worst case control-to-output gain response pole at minimum load (maximum resistance load)

wp = 2 / ( RLmax * Co ) = 2 / ( 500 * 6.8 * 10^-4 ) = 5.882 radians or approx 1HZ.

To make our equations a little easier to type here let me make the following substitutions:

Z1 = 1 + ( S / wz ) where S is the complex operator = j * 2 * Pi * f (using only the imaginary component of S in this work.)

P1 = 1 + ( S / wp )

The values of Z1 and P1 are only dummy variables and not actual frequencies, but their values will be different at different frequencies. Also note here that because we always operate in discontinuous current mode (DCM), we do not have to worry about a right-half plane zero which would otherwise be present if we were operating in continuous current mode (CCM.)

We can now type a simple equation for the control-to-output gain as a function of frequency as follows:

Gco = ( Vo / VFB ) * ( Z1 / P1 )

where Vo is the nominal output voltage ( 5 volts ) and VFB is the nominal feedback voltage ( 2.5 volts .) A plot of the control-to-output gain is shown in the post.

Next we have a simple compensation network that is similar to the ones used in most flyback converters of this type. The purpose of the compensation network is to make the system stable with a reasonable control band-width and known feedback characteristics, such as cross-over frequency, phase and gain margins.

First we compute the constant gain factor K as

K = RB / ( R1 * RD * CF ) = 1000 / ( 5360 * 100 * 1 * 10^-6 ) = 1866

where RB is the PWM controller IC feedback input impedance (we added a 1K to ground at the ouput of opto-coupler to establish a known value for this quantity.) RD is the feedback amplifier IC collector resistance, and CF is the compensation capacitance for this amplifier.

We need to have a compensation zero to help cancel the converter pole at 1 HZ. But the compensation pole will be set at approximately 15HZ:

wzc = 1 / ( ( RF + R1 ) * CF ) = 1 / ( ( 5100 + 5360 ) * 1 *10^-6 ) = 95.6 radians
or 15.2 HZ.

Also we need to set a compensation pole. We will set this pole at a relatively high frequency in order to flatten over-all loop gain and establish reasonable bandwidth.

wpc = 1 / ( RB * CB ) = 1 / ( 1000 * 1 * 10^-8 ) = 100000 radians

or 15920 HZ ( still well below the switching frequency of 100KHZ.)

Now for convenience in typing the compensation equation we will set some dummy variables as

Zc = 1 + ( S / wzc )

and

Pc = 1 + ( 1 / wpc )

We can now write a simple equation for the compensation gain as a function of frequency as

Gc = - ( K / S ) * ( Zc / Pc )

In the above equation we note that the negative sign is because we are using negative feedback in the compensation circuit to control the converter.

Now it is known that the overall loop gain, that is the gain of the converter from its input around to the feedback input at the IC controller can be computed from the product of the control-to-output gain and the compensation gain as

Gol = Gco * Gc

The results of the calculation vs. frequency is shown in the chart for the loop gain. The calculations can be done by math programs such as Mathcad, etc.

You will note that the loop gain has a cross-over frequency of approximately 40HZ (which could probably be improved a lot with some improvements to the compensation circuit.) The loop gain at DC is pretty good at over 50DB and the cross-over slope is -20db per decade indicating absolute stability (this is also verified by SPICE simulation of the closed loop circuit of Fig. 1.) The phase shift is a little over 70 degrees at crossover which gives us a phase margin of 110 degrees which also indicates absolute stability. So this converter is a relatively low bandwidth design but should be very stable over all operating conditions that wre within its specifications. The fact that it operates in DCM also helps simplify stabilization, but this is not to say that we should always operate in DCM. In fact, if the converter had been designed as a CCM type, it would be capable of more power and peak ripple current in the output filter capacitor could be reduced.

FLYBACK CALCULATIONS - PART VII

In this section we will discuss the snubber network for the transistor switch on the primary side of the converter (see Fig.1. Click on the figure to see a larger view.) First an estimate is made for the voltage spike that is to be snubbed as 2.5 times the reflected voltage from the secondary as

Vsn = 2.5 * VRO

With VRO previously determined to be 350 volts (see previous posts), we have

Vsn = 875 volts

Next we use this estimate to calculate an approximate value for the power dissipated in the snubber network.

Psn = 0.5 * Fs * Llk * Idspeak^2 * Vsn / (Vsn -VRO)

where Fs is the switching frequency, Llk is the transformer leakage inductance, and Idspeak is the peak transistor switch current. Our calculation results in

Psn = 0.316 watts

where the data we used is from our design example as

Fs = 100KHZ
Llk = 141 microhenry
Idspeak = 0.164

Now we can calculate a rough estimate of what the snubber resistor value should be (usually it is necessary to change the value based on actual snubber network performance but it gives us a starting point.)

Rsn = Vsn^2 / Psn = 2.4 megohm

(In the actual design, this resistor was changed to 360K.)

Using the 2.4 megohm value for the snubber resistor we will calculate the ripple voltage on the capacitor we have


dVsn = Vsn / ( Csn * Rsn * Fs ) = 3.6 volts

with Csn set to 0.001 microfarad. Note that if the value of Csn is set too hihg the operation of the flyback converter will not work well, e.g., values above 0.01 microfarad usually do not provide good results depending on the other values used in the design such as the primary inductance value. Remember that the primary inductance and the snubber capacitor form a "tank" circuit that can resonate and this is not usually desirable in a standard flyback converter.

We now have a preliminary design for the snubber network.

FLYBACK CALCULATIONS - PART VI

In this part we will calculate the RMS current ripple in the main output filter capacitor.

First we need to calculate the main output secondary current using the following data:

Idrms = 0.2 A
Dmax = 0.85
VRO = 350 volts
KL = 1.0
VF1 = 1.0 volt
Vo1 = 14 volts

where Idrms is the rms transistor switch current, Dmax is the maximum allowable duty cycle (usually limited by the main PWM control IC), VRO is the secondary voltage reflected to the primary side, Vo1 is the nominal output voltage, VF1 is the forward voltage of the output diode, and KL is the load occupying factor for the main output (1.0 if there is only one output winding.)

The equation for the secondary RMS current is

Isecrms = Idsrms * (((1 - Dmax) / Dmax )^0.5) * VRO * KL / (Vo1 + VF1)

Isecrms = 1.96 A

The output current Io is specified as 0.3 amps, so now we can calculate the output capacitor ripple current. This current is usually inconveniently large for flyback converters and cheap converters are sometimes found to have an output filter capacitor that is under-rated for ripple current. The risk is that the capacitor will overheat, dry-out too fast and the converter will fail to operate as intended. The ripple current is calculated as follows:


Icaprms = ( Isecrms^2 - Io^2 )^0.5

Icaprms = 2.28 A

Note that a continuous current mode (CCM) converter will have a lower secondary RMS current for a given output current load.

So we will need to have a capacitor that is rated at 2.3 amps or better for this design. It is better to use one large capacitor instead of smaller capacitors in parallel to meet the current requirement as parallel capacitors will not necessarily share ripple current equally and one or more of them could overheat. It is usually good though to put small capacitors in parallel such as ceramic chip caps for filtering high frequency noise.

Assume that we have the additional data as follows:


Co = 330UFD

Rc = 0.07 ohm

Idspeak = 0.3 A

Fs = 100KHZ

where Co is the output filter capacitance total, Rc is the equivalent series resistance of the capacitance, Idspeak is the peak transistor switch current, and Fs is the converter switching frequency.

Now we can calculate the theoretical output ripple or noise voltage using the equation

dVo1 = Io * Dmax / (Co * Fs ) + Idspeak * VRO * Rc * KL / (Vo1 + VF1 )

dVo1 = 0.498 volts

On an output voltage of 14 volts, 0.498 volts is about 3.6%. This value is probably OK for a battery charger converter, but probably too high if the voltage is to be used to power some electronic circuit. For a lower output ripple voltage, it would be necessary to increase capacitance value, reduce the equivalent series resistance of the capacitor, or both. Notice that the above calculation ignores the effects of the capacitor series inductance and the inductance of the circuit wires or circuit board traces. A low inductance layout is very important to keep noise low.

AC-DC FLYBACK CALCULATIONS - PART V

One of the most important things to determine on the AC-DC flyback converter are the RMS secondary winding currents. The RMS current must be filtered by a capacitor which is usually an aluminum electrolytic capacitor or some type of large capacitance high ripple current capable capacitor. One of the main failure modes of poorly designed flyback converters is an inadequate current rating for the filter capacitors. If the output capacitor is over-stressed with ripple current beyond its ratings it will run hot, dry out if it is a wet electrolytic, and otherwise fail casuing converter failure.

We can calculate the RMS current for each secondary winding according to a simple formula as follows:

Isecrms = Idsrms * (( 1 - Dmax ) / Dmax )^0.5 * VRO * KL / ( Vo1 + Vf1 )

where we have previously calculated the rms switch current Idsrms = 0.234 A, VRO = 349 volts, and we have specified Vo1 = 14 volts, Vf1 = 1 volts, and the load occupying factor KL has been set to 0.8 or 80% of the total load on the Vo1 output.

The answer is then that Isecrms = 1.8 amps. This is not a trival amount of ripple current to deal with and it will require a large electroylitic capacitor or several capacitors in parallel to handle the current. Note that it is difficult to parallel capaciotrs to handle the total load because one capacitor will more than likely try to handle most of the load and overheat while the other ones are not handling their share.

Another thing to be concerned about in flyback converters is the rating of the diode that feeds current to the filter capacitor from the secondary winding (see Fig. 1 -click on the figure for a larger view.) The current rating of the diode must be able to handle the RMS current we just calculated above and it must have a high enough voltage rating to handle the reverse spikes which are present on every switch cycle of the converter. We can calculate the reverse voltage on the diode from the following formula:

Vdr = Vo1 + Vdcmax * ( Vo1 + Vf1 ) / VRO

where Vo1 is the output DC voltage, 14V, Vdcmax is the max input voltage, 1000V,
Vf1 is the forward diode voltage, 1 volt, and VRO is the voltage reflected from secondary to primary on each switch cycle, 349 volts.

Vdr = 56.9 volts

is the peak reverse voltage on the diode.

It is customary to comput the VRRM (the voltage rating reverse maximum value) as

VRRM = 1.3 * Vdr = 74 volts

The VRRM value we computed is beyond the normal max for schottky diodes of 45 volts but there are some hybrid schottkys that will rate higher. The advantage of schottky diodes is that they have a lower forward voltage drop and therefor dissipate less heat and power for a given current load. If the output voltage had been 5 volts instead of 14, we could then have used a 35V or 45V schottky diode as VRRM would have calculated to 29 volts.

FLYBACK CALCULATIONS - PART IV

In all switchmode converters that use a high frequency switching inductor or transformer, such as the typical AC-DC flyback converter shown if Fig. 1, it is of critical importance to avoid saturation of the inductor or transformer. If saturation occurs, the inductance of the transformer or inductor will decrease greatly so that the windings will no longer support the applied voltage. If saturation occurs when the transistor switch is in the on-state, the switch current is theoretically unlimited and this could lead to destruction of the converter. Even when current mode control is used, the initial turn-on spike will be so large that it most likely will cause the switch to fail.

To avoid going into saturation, the transformer must be designed so that at maximum current (set by the current limit), the transformer or inductor will not saturate. Therefore we need to determine the maximum magnetic field density (flux density) that the transformer core material will support (carefully the core manufacturer's data sheet), the effective cross-sectional area of the core, the inductance of the inductor or the primary of the transformer, and the maximum current set by the current limit. Then we must calculate the minimum number of inductor or primary turns that will be required to avoid saturation. The number of turns required is directly proportional to the product of the inductance and the maximum current and inversely proportional to the product of the maximum flux density and the core area.

Npmin = Lm * Ilim * 10^6 / ( Bsat * Ae )

Let

Lm = 0.007 Henry

Ilim = 0.200 Ampere

Ae = 31.5 mm^2

Bsat = 0.25 Tesla ( 2500 Gauss )

Then

Np = 187 turns ( rounded up to the nearest full turn )

The actual design might use 225 turns to provide a safety factor of approximately 20%.

Once we have set the primary turns, we can then calculate the turns ratio that is needed to achieve the required main output (the controlled output) voltage as


n = VRO / ( Vo1 + vf1 )


Let

VRO = 350 volts

Vo1 = 15 volts

Vf1 = 1 volt

where VRO is the reflected voltage from secondary to primary (previously calculated in the post, Flyback Calculations - Part I), Vo1 is the required main output voltage, and Vf1 is the forward voltage of the output rectifier diode at maximum output current. Then

n = 22 (rounded to an integer)

Now it is easy to compute the required turns of the main secondary, as


Ns1 = Np / n = 10 (rounded to the closest integer)

The other secondary output turns can now be computed using the values from the equation

Nox = ( Vox + Vfx ) * Ns1 / ( Vo1 + Vf1 )

where Nox is the required secondary turns, Vfx is its diode forward voltage at the winding's maximum current. For example if Vox is 125 volts and Vfx is 1.2 volts, we have

Nox = 81 turns (rounded up to the nearest integer )

We can also note here that secondaries in this transformer design are roughly 1.5 volts per turn. This is a reasonable value for the design. A practical range for secondary volts per turn is usually 1 to 2 volts per turn.

FLYBACK CALCULTIONS - PART III

This post will calculate the current ripple factor from the peak current step IEDC,
the smaller ramp on top of the current pulse which we will call dl, and the RMS current. Fig. 1 shows the general topology of the converter.

First we calculate IEDC

IEDC = Pin / ( Vdcmin * Dmax )

Assume that Pin is 5.8 watts, Vdcmin is 50 volts and Dmax is 86% or 0.86. Calculating IEDC we get

IEDC = 0.135 Amp

This is the first component or major step of the peak current pulse.

The above calculation is the worst case value at maximum duty cycle, maximum input power required, and the worst case minimum input voltage. Note that you will get higher peak currents as D is reduced and Vdcmin is reduced for a given power input value.

We will also calculate the equivalent RMS current, which we will consider below.

Now we need to calculate the second component or ramp of the current pulse, dl

dl = Vdcmin * Dmax / ( Lm * Fs )

Assume that Lm is 0.007 Henry, and Fs is 100KHZ. Then


dl = 0.058 Amp


We can now calculate the Current Ripple Factor, KRF as

KRF = dl / ( 2 * IEDC ) = 0.215

The point of the above calculations is to determine whether the converter will operate in Discontinuous Current Mode (DCM) or in Continuous Current Mode (CCM). When KRF is less than unity, the converter is operating in CCM at minimum voltage input and maximum duty cycle with the specified maximum power input required.

With the results of the above calculations, we can also calculate the equivalent peak current in the transistor switch as

Idspeak = IEDC + ( dl / 2 ) = 0.164 Amp

Next we calculate the theoretical RMS current for the inductor and transistor from


Idsrms = ( 3 * IEDC^2 + dl^2 * ( Dmax / 12 ) )^0.5 = 0.234 watt


This is the current to use when calculating RMS current in the transistor and switching transformer.

DESIGNING AN AC-DC FLYBACK CONVERTER - PART II

One important thing to know about your flyback converter is whether it will mainly operate in continuous current mode (CCM) or discontinuous current mode (DCM.) For the highest power output per cubic inch, lowest noise, and lower peak currents, CCM is the choice (and most commercial converters are CCM.)

The advantage of DCM is that their is no right-half plane zero in the gain vs. frequency response which is difficult to compensate for. In the CCM condition there is a right-half zero so the bandwidth of the converter must be limited so that the zero does not cause instability.

The use of current limiting in modern converters helps to maintain stability and simplifies design of the feedback compensation network. We will discuss the feedback compensation and design of the feedback network in a later post.

Most practical flyback converters will operate in both CCM and DCM (but not at the same time) if conditions are allowed to put the converter into one mode or the other. Some converters are designed to operate right on the boundary between CCM and DCM.

You can find the operating point of your converter under operating conditions by calculation of the value of the minimum input voltage to maintain DCM which is also the maximum input to maintain CCM operation. This point depends on primary inductance, operating frequency, power required at the input, and the reflected voltage on the primary from the secondary, as well as other factors which we will ignore in this calculation:

Vdccm = ( ( 1 / ( 2 * Lp * Fs * Pin )) - ( 1 / VRO) )^-1

As a practical example, suppose that

VRO = 350 volts

Lp = 0.007 H

Fs = 100000HZ

Pin = 5.8 watts

Then

Vdccm = 126 volts approximately.

So 126 volts is the minimum input voltage to maintain DCM operation. A lower input voltage will force this converter design into CCM operation.

Or conversely, if the input voltage is higher than 126 volts, you cannot maintain CCm operation and you will be operating in DCM mode.