Mutiphase Buck Converters

My notebook drawing above shows what might be a typical multiphase buck converter as a simplified block diagram of what a 3-phase system might be like (I don't claim to have inverted this.) The basic elements are a master control IC, slave gate drivers 1, 2, 3, and mosfet switches Q1-Q6. In a real implementation, the mosfet switches and gate drivers might be combined into one IC. One example similar to my drawing is the International Rectifier (TM) part iP2001. The main control IC usually has the basic functions of PWM signal generation, current and voltage sensing, frequency compensation, and some type of control bus which could be simply a set of external switches set to pull certain control bits up or down, an external microprocessor, or a serial bus such as an IC square (TM) or combinations of control methods. Each set of gate driver and pair of mosfets act like a separate high frequency synchronous buck converter as described in my previous article.

The three buck converters are paralleled into one system to form the 3-phase converter. Each phase operates in sync with the other phases at say 500KHZ each so the effective switching frequency is 1.5MHZ. Current is balanced in each phase by sensing the current in each inductor through the resistors R1, R2, and R3. Sometimes the current is determined by sensing the voltage drops across the upper mosfet in each pair, or by sensing the average current through the inductor. Inductors L1, L2, and L3 can be coupled for lower noise output. A complete description of the theory of coupling for lower noise is beyond the scope of the present article. Capacitors C1, C2, C3 represent possibly many capacitors in parallel that serve to filter noise and stabilize the converter. The inductance value, L1, for example and the effective capacitance C as the sum of all the capacitors set the pole and bandwidth of the converter as 1/(2*Pi*sqrt(L*C)) before compensation. The compensation network might be similar to the resistor-capacitor network shown between pins VSENS, FB, and COMP. Typical operating conditions could be a 12V input (Vi) and a 1.1 to 2V output at high currents. The 3-phase converter shown above could be capable of 60 amps output or more depending on the component ratings. The author designed and tested a 4-phase converter capable of 100 amps output at 1.2 volts with less than 15mv peak-to-peak noise. The typical application would be to power a low voltage microprocessor, graphics processor, or other processors that require large currents with high speed current demand pulses with low noise.

What is a Synchronous Buck Converter?

Fig. 1 shows a simplified synchronous buck converter circuit. U1 is what is called a “synchronous buck controller” because of its capability to control the power switches Q1 and Q2 in a synchronous fashion using its gate drive output labeled HG and LG in Fig. 1. The controller may have additional functions not shown in Fig. 1, such as a “boot” voltage input to be able to drive Q1’s gate with a drive voltage signal above the input power rail to insure that the switch will turn on. The boot voltage may be derived from the switching node S1 or from a VCC supply voltage that is sufficiently higher than the power rail voltage.

U1 may also have a way of sensing current into S1 or through the high side mosfet Q1 or through the inductor L. Sometimes the voltage drop across Q1 is used to monitor current. The circuit may then be operated in current mode control (see my previously posted article for a description of current mode control.)

The circuit is called synchronous because the top switch is turned on when the bottom switch is turned off and vice versa. This eliminates the power loss in a diode that would otherwise need to be used in place of Q1. Of course, there cannot be any significant overlap of the on-times of Q1 and Q2 or there will be what is called “cross-conduction” which will cause heating, power loss, and possible failure of the switches due to over-current. On the other hand, there should not be too much dead time or a large Q1 turn-off voltage spike will occur at the open end of the inductor possibly causing switch failure or damage to U1.

The LC filter removes noise and ripple voltage from the output. R1 and R2 adjust the feedback voltage level to be compatible with the internal voltage reference included in U1. R3, R4, and C2 form a typical feedback compensation network. Note that the equivalent series resistance (ESR) of the filter capacitor C is important in determining the compensation network, and of course also affects the amount of noise that is seen at the output. ( See also my first article posted for the main equations governing the buck circuit.)

What is current mode control?

How does current mode control work? Referring to Fig. 1, the block SW represents the power switching stage of a PWM converter (see previously posted article.) HC is the inner current control loop which converts the sensed current into a voltage signal that represents the magnitude of each current pulse generated by the switching stage. In this way we can achieve pulse-by-pulse current control. Pulse-by-pulse control allows very rapid response to over-current or fault conditions. The current sensed is usually the current ramp that enters and energizes the inductor. This energy will later be dumped into the filter capacitor C which filters output voltage ripple. The LC filter generates two poles in the transfer function which need to be dealt with by the feedback control and compensation system. One of the advantages of the current control method is that it tends to nullify one of the inductor poles so that the outside voltage control loop can have simplified compensation for the error amplifier A (see the URL listed below for more information on operational amplifiers and feedback.)

The outer voltage control loop senses a ratio of the output voltage, using the voltage divider R1 and R2. This voltage is compared to the voltage reference applied as one of the inputs to the error amplifier. The error amplifier may have compensation elements Z1 and Z2 in Fig. 1, but with the current mode control inner loop, the compensation can usually be simplified to a simple RC net for Z2 and just a resistor for Z1. The output of the voltage error amplifier is summed together with the current sense signal to control the operation of the converter. The two control loops provide excellent control of the system when properly designed.

One caution is that for higher duty cycles, a sub-harmonic or low frequency oscillation may occur. Fortunately there is a cure for this problem called slope compensation that adds some slope to the current sense ramp to prevent the instability. Excellent articles on this subject are provided by Venable ™, Ridley Engineering ™, and Texas Instruments ™.

There are also good current mode control integrated circuits that combine circuits for both the current mode control and voltage mode control loops. These IC’s are available from Texas Instruments ™, Linear Technology ™, and other companies. You may want to look-up the datasheet for an IC made by Texas Instruments ™ by the part number UC1842. This family of IC’s is the grand-daddy of current mode control IC’s and is still available. It also available from a number of manufacturers and distributors.

http://analogelectronix.blogspot.com

What is Pulse Width Modulation?

How does pulse width modulation work? Referring to Fig. 1, the classical method of voltage mode PWM is to compare an error signal to a reference ramp oscillator waveform as shown in Fig. 1. In the figure, as the error signal crosses the rising edge of the ramp, the comparator output goes to its high output level, and conversely when the error signal crosses the falling edge of the ramp, the comparator switches to its low level output.

Also, if we wish the duty cycle to increase when the error signal falls, to correct the system output, or increase system output, such as the voltage of a regulated converter, or the speed of a motor, for example, the example of Fig. 1 shows exactly that effect. As the error signal drops, the pulse width increases, thereby applying more power, or voltage, or more signal level to the load.

Why do we convert the error signal to a PWM signal? Because the PWM signal can operate an electronic switch such as a mosfet or a transistor that will rapidly switch on and off and transfer power more efficiently. The comparator output, if it is 0 to 5 volts or higher, can drive the gate of a power mosfet directly thereby controlling a lot of power with a small signal. If needed, the output signal of the comparator can be buffered with a high current buffer pulse amplifier to allow the ability to drive very large transistor switches and even paralleled transistor switches for high power.

The Basic Buck Converter

A simple single switch buck converter is shown in Fig. 1. Because of the power loss in the diode D1, the single switch buck converter is not suitable for high current or high power applications. It would work, however, with suitable choice of components, for low power, low current, and low voltage applications. If the input voltage is less than 40 volts, D1 could be a Schottky diode to improve efficiency. Not shown in Fig. 1 is the method of developing the high frequency pulse drive signal which is usually a type of pulse width modulated (PWM) signal that drives Q1 either into a saturated-on condition of a fully turned off condition. As long as Q1 is either in the full on or full off state, alternately at the converter switching frequency, the power dissipation in Q1 will be relatively low as power is dissipated only during the times that current is flowing through the switch when voltage across the switch is not close to zero. There are some other losses in Q1 which are also present which we will discuss in another article.

We can define the duty cycle D at any given time as the ratio of the time the switch is on to the total time of the each switching cycle (also called the switching period.)

D = Ton / Tsw

The switching frequency can be constant or variable, but it is usually relatively constant under steady state conditions can be calculated as

Fsw = 1 / Tsw

The output voltage is set by the duty cycle and the input voltage under steady state conditions as

Vout = D*Vin = Vin * Ton / Tsw

The maximum or peak voltage, Vds, across the mosfet Q1, drain to source is

Vds = Vin + Vd

where Vd is the forward voltage of the diode. The function of the diode is to allow current to continue flowing to the load when Q1 is in the off state. The peak Q1 drain current is

Idrain = I_load + dIp_inductor / 2

where dIp_inductor is the peak inductor current above the DC load current and can be calculated as

dIp_inductor = Vin * Ton /L

where L is the inductance value in Henries. We note here that the capacitor C1 has to be rated to handle the ripple current from the inductor, and of course be rated for the output output voltage. If C1 is a tantalum capacitor, it is usually de-rated by 50% for the output voltage of the converter.

Finally, the diode average current can be computed as

Id = I_load*(1-D)

The diode has to be rated to handle the input voltage and its average current.

We have now covered the basic calculations for the single switch buck converter which would allow a power stage to be designed with selection of components for the application. We should also note that the buck converter is used only to reduce some input or bus DC voltage down to a lower DC voltage. We have not yet covered drive signal generation (PWM) for Q1 gate drive, nor the control network which is usually a feedback loop with frequency compensation elements.